Amstrad PCW Hardware Reference

This is an incomplete guide to the hardware of Amstrad's original PCW series - the 8256/8512, 9256/9512, and 10. It does not cover the PCW16.

Sources include "All you ever wanted to know..." by CP Software, John Elliott, Jacob Nevins (and his excellent web pages), Cliff Lawson (who kindly OCRed the original Amstrad documentation), Howard Fisher (who lent me a KeyMouse), Paul Hunt, and Kevin Thacker's CPC resource, which contains Z80 and FDC info relevant to the PCW. Thanks chaps. Further information is always welcome.

Richard Fairhurst, 1996-1997

Introduction

The PCW's operating system is CP/M, which is comprised of two main parts.

The BDOS (Basic Disc Operating System) is the actual OS code itself, written by Digital Research. This should largely remain the same for any machine running CP/M.

The BIOS (Basic Input/Output System) provides a set of routines which access the machine's hardware, and was written in the PCW's case by Locomotive/Amstrad. The BIOS routines are called by the BDOS for all screen, disc, and printer operations.

Also relevant is the CCP (Command Console Processor), the front-end which accepts commands typed at the A> prompt. The PCW's implementation of CP/M only loads this on system startup, so it must not be overwritten.

The TPA (Transient Program Area) is the area of memory, starting at &0100 in a 64k address space, where user programs (.COM files) load and run.

I/O ports

External hardware/FDC

&00I FDC status register
&01I/O FDC data register
&88-&8F Parallel ports
&9FI Kempston joystick
&A0I AMX mouse. Vertical movement: b0-3 4-bit up counter, b4-7 down counter.
&A1I AMX mouse. Horizontal movement: b0-3 4-bit right counter, b4-7 left counter.
&A2I AMX mouse. Button states: b2 right, b1 middle, b0 left (0 if pressed, 1 if not).
&A0-&A2EMR MIDI interface
&A8-&AFHard drive
&C8-&CFI/O Fax Link interface (CPS8256-compatible circuitry).
&D0-&D4Kempston mouse (similar to AMX)
&DFI MasterScan: b0 ink under scan head.
&E0I Cascade/Spectravideo joystick. b4 right, b3 up, b2 left, b1 fire, b0 down.
&E0-&EFI/O Serial ports (click for more)

Internal ports

&F0O Select bank for &0000
&F1O Select bank for &4000
&F2O Select bank for &8000
&F3O Select bank for &C000. Usually &87.
&F4O b7-b4: when set, force memory reads to access the same bank as writes for &C000, &0000, &8000, and &4000 respectively
&F4I As &F8, with the proviso that b3-0 are reset when the port is read. Hence read to re-enable interrupts.
&F5O Address of roller RAM. b7-5: bank (0-7). b4-1: address / 512.
&F6O Vertical screen position
&F7O b7: reverse video. b6: screen enable.
&F8O0 end bootstrap, 1 reboot, 2/3/4 connect FDC to NMI/standard interrupts/neither, 5/6 set/clear FDC terminal count, 7/8 screen on/off (for external video), 9/10 disc motor on/off, 11/12 beep on/off
&F8Ib6: 1 line flyback, read twice in succession indicates frame flyback. b5: FDC interrupt. b4: indicates 32-line screen. b3-0: 300Hz interrupt counter: stays at 1111 until reset by in a,(&F4) (see above).
&FC-&FD Parallel port (PCW9512)
&FCI/O Matrix printer data
&FDOMatrix printer commands
&FDIMatrix printer status. b7 bailbar (0 out), b2 paper found.

Unlike the CPC, the PCW uses the standard Z80 method of accessing I/O ports. Either the port is stored as a (single-byte) number in C and an instruction like out (c),a used, or the port is passed as part of the instruction out (&port),a.

Interrupts/clock speed

Interrupts occur 300 times a second, or 6 times per frame (as on the CPC), at 2 scan lines into frame flyback and every 52 lines thereafter. Frame flyback can be sensed by reading port &F8 twice in succession. Only if b6 is set each time is the PCW in frame flyback.

The PCW's clock speed is 3.4MHz, slowed down from a 4MHz CPU. However, access by the video hardware slows down memory accesses to the first 128k (banks 0-7). The BIOS interrupt is also slow, and should be disabled for time-critical operations where operations such as keyboard scanning and disc access are not required.

Memory map

The PCW 8256 has 16 banks of 16k each. 512k and expanded machines obviously contain more. The default contents are:

0&0000-&3FFF: BIOS, extended jumpblock
1&0000-&192F: BIOS
&1930-&3FFF: screen
2&0000-&332F: screen
&3600-&37FF: roller RAM
&3800-&3FFF: character set
3&0000-&3FEF: BIOS, BDOS
&3FF0-&3FFF: DMA keyboard map
4&0000-&00FF: workspace and BIOS/BDOS jumps
&0100-&3FFF: TPA
5&0000-&3FFF: TPA
6&0000-&3FFF: TPA
7&0000-&2FFF: common RAM (available for use under all configurations)
&3000-&3FFF: CP/M workspace
8&0000-&3FFF: CCP, hash tables, data buffers
9-16 &0000-&3FFF: RAM-disc (drive M:)

The roller RAM and screen memory may be stored in any of banks 0-7. Consequently, video circuitry access requirements slow down any code/data access in these banks.

Any bank can be mapped into any of the four 16k segments of the Z80's address space using ports &F0-&F3. Under CP/M, the following (named) arrangements are standard:

ScreenBDOS (0)Extra (n+2)TPA (1)
&C000 (&F3) 7 common 7 common 7 common 7 common
&8000 (&F2) 2 screen 3 BDOS/BIOS 3 BDOS/BIOS 6 TPA
&4000 (&F1) 1 screen/BIOS1 screen/BIOS 8+n CCP or M: 5 TPA
&0000 (&F0) 0 BIOS 0 BIOS 0 BIOS 4 TPA

Sending the bank number (with b7 set) to one of ports &F0-&F3 selects that bank for reading and writing. Sending the bank number for writing to b0-2 of a port and the bank for reading to b4-b6 (with b7 reset) maps separate banks in for reading and writing: this can only be used for the first 8 banks.

As an example of read/write access, to map bank 5 into memory from &4000, you would use ld a,&85: out (&F1),a.

Screen memory

The PCW screen on 50Hz (non-US) models is 90x32 characters, or 720x256 pixels. Each pixel line can begin at any address within the first 128k of memory: the address of each line is stored in a 512-byte area of memory known as the roller RAM. By default, the roller RAM is located at &3600 (mapped to &B600) in bank 2, but this may be changed using port &F5. It contains 256 consecutive addresses, stored in the usual Z80 low byte first format: b16-14 control which bank the line is to be found in, b13-3 the address in the bank (in 16-byte units), and b2-0 the offset. Thus a roller RAM address bbbxxxxxxxxxxxyyy indicates bank bbb, address 00xxxxxxxxxxx0yyy.

Each line is 720, not 90 bytes long. This is because the PCW takes every eighth byte starting at the address pointed to by the roller RAM. In this way, eight screen lines may be interleaved as follows for easy character writing (assuming a consecutive roller RAM arrangement):

        (a+0)   (a+8)   (a+16)  ...
        (a+1)   (a+9)   (a+17)
        (a+2)   (a+10)  (a+18)
        (a+3)   (a+11)  (a+19)
        (a+4)   (a+12)  (a+20)
        (a+5)   (a+13)  (a+21)
        (a+6)   (a+14)  (a+22)
        (a+7)   (a+15)  (a+23)

The vertical position of the screen on the monitor may be altered by incrementing or decrementing port &F6.

Keyboard mapping

The PCW's keyboard is directly mapped into the last 16 bytes of bank 3, even when interrupts are disabled. Each key is reflected by one bit in bytes &3FF0-&3FFA.

b7:   k2     k1     [+]    .      ,      space  V      X      Z      del<   alt
b6:   k3     k5     1/2    /      M      N      B      C      lock          k.
b5:   k6     k4     shift  ;      K      J      F      D      A             enter
b4:   k9     k8     k7           L      H      G      S      tab           f8
b3:   paste  copy   #      P      I      Y      T      W      Q             [-]
b2:   f2     cut    return [      O      U      R      E      stop          can
b1:   k0     ptr    ]      -      9      7      5      3      2             extra
b0:   f4     exit   del>   =      0      8      6      4      1             f6
      &3FF0  &3FF1  &3FF2  &3FF3  &3FF4  &3FF5  &3FF6  &3FF7  &3FF8  &3FF9  &3FFA
Bytes &3FFB-&3FFF reflect the keyboard in a different, incomplete way. These bytes are also used by Creative Technology's KeyMouse (in its standard "MicroDesign mode") and the Teqniche 102-key keyboard to provide additional functionality, creating some incompatibilities along the way. Among the more interesting mappings are the following:

&3FFB Standard keyboard  
KeyMouse
b7-b0 unused (0)
b6-b0 horizontal movement counter.
&3FFC KeyMouse b7-b6 high bits of vertical movement counter.
&3FFD All
Standard keyboard
KeyMouse
b7 always set; b6 current state of SHIFT LOCK
b3-b0 cursor keys, b4 matrix key
b3-b0 low bits of vertical movement counter.
&3FFE KeyMouse b7 left button, b6 right button.