Amstrad CPS8256 Technical Reference
Sources for this document are two PD text files, DART.DOC (by SJ Dibble) and AMS-SIO.DAT, covering the serial port only. Information on the parallel port, and on any other serial/parallel interfaces, would be appreciated.
Richard Fairhurst, 1997
Port addresses
The following I/O addresses are used by the CPS8256. For reference, the equivalent ports on Amstrad, Pace and Cirkit interfaces for the CPC are included in brackets.
&E0 (&FADC) | DART data |
&E1 (&FADD) | DART control |
&E2 (&FADE) | DART data (port B) |
&E3 (&FADF) | DART control (port B) |
&E4 (&FBDC) | 8253 counter 0 |
&E5 (&FBDD) | 8253 counter 1 |
&E6 (&FBDE) | unused |
&E7 (&FBDF) | 8253 write mode word |
Baud rates
To set the transmit rate, send &36 to port &E7, and two values from the table (in the order given) to &E4. To set the receive rate, replace &36 with &76. This values are obtained with the CTC 8253 connected to 1.84375MHz.
Note that the 8250 is only reliable at speeds up to 9600 baud. To use faster speeds, you should replace it with a 16550AF chip, which is pin-compatible with the 8250. (Thanks to Rob Scott for this information.)
| 31250 | &00, &04 |
| 19200 | &00, &07 |
| 9600 | &00, &0D |
| 7200 | &00, &11 |
| 4800 | &00, &1A |
| 3600 | &00, &23 |
| 2400 | &00, &34 |
| 2000 | &00, &3F |
| 1800 | &00, &45 |
| 1200 | &00, &68 |
| 600 | &00, &D0 |
| 300 | &01, &A0 |
| 200 | &02, &71 |
| 150 | &03, &41 |
| 110 | &04, &70 |
| 75 | &06, &83 |
| 50 | &09, &C4 |
| 45 | &0A, &D9 |
DART registers
Other control functions involve programming the DART. To write a value to a register, first send the register number, then the new value, to &E1. To read a value, output the register number, and then you can input it from the same port.
Write register 0
&18: reset port
&38: reset error bits
Write register 3
b7 and b6: Rx data bits (11 8 bits, 10 7, 01 6, 00 5)
b5: hardware handshaking using RTS/CTS
b4 to b1: must be 0
b0: enable Rx data line
Write register 4
b7 and b6: DART clock mode (set to 01)
b5 and b4: unused (set to 0)
b3 and b2: stop bits (11 2 bits, 10 1, 01 1.5, 00 illegal)
b1: parity type (1 even, 0 odd)
b0: parity checking on/off
Write register 5
b7: DTR enabled/disabled
b6 and b5: Tx data bits (11 8 bits, 10 7, 01 6, 00 5)
b4: send break
b3: enable Tx data line
b2: unused
b1: RTS enabled/disabled
b0: unused
Read register 0
b7: break received
b6: unused
b5: CTS
b4: ring indicate
b3: DCD (carrier detect)
b2: Tx buffer ready
b1: interrupt-related
b0: Rx character available
Read register 1
b7: unused
b6: framing error
b5: Rx overrun error
b4: parity error
b3 to b1: unused
b0: all sent